The present invention relates generally to memory devices. More specifically, the present invention relates to method and apparatus for activating such memory devices.
FIG. 1A is a diagrammatic representation of a conventional memory device 100. As shown, the memory device 100 is configured to receive a plurality of address (ADR) signals, a clock signal (CLK), and a combined read and write enable (WR!/RD) signal. An "!" denotes that a write operation is enabled when the WR!/RD signal has a low value, while a high value enables a read operation. The memory device is also coupled with a databus (DB) that is used for receiving and outputting data into and out of the memory device 100.
Conventional memory devices typically include a memory array for storing data and a decoder for receiving the plurality of address signals and activating a particular memory location within the memory array that is associated with the address signals. The WR!/RD input signal indicates whether data is being retrieved from or input to the specified memory location of the memory array. Additionally, the memory device 100 uses the CLK signal to enable activation of the specified memory location.
Currently, memory devices typically are configured to follow one of two approaches for enabling the memory array: enabling during a rising edge of the CLK signal or enabling during a falling edge of the CLK signal. For both approaches, the memory device is configured to use the received CLK signal to enable activation of the specified memory location. These two conventional approaches are described below in reference to FIGS. 1B.
FIG. 1B represents typical timing diagrams for CLK and ADR signals (ADR.sub.1 through ADR.sub.n), which are provided to the memory device 100 of FIG. 1A. As described above, the memory device 100 is enabled either during the rising edge 102 or the falling edge 104 of the CLK signal. When the memory device 100 is enabled (e.g., during transition 102 or 104), the specified memory location is then activated and data is read from or written to the specified memory location within the memory array.
Although these two conventional enabling approaches work well under certain conditions, both approaches have associated disadvantages. When the memory device is enabled at the CLK signal's rising edge 104, all or some of the ADR signals may have failed to completely transition to their new address values before the specified memory location is activated. The ADR signals typically begin to transition from a first value to a second value at the rising edge of the CLK signal. However, some of the ADR signals take a significantly longer time to transition than other address signals. As shown, the transition times for ADR.sub.1, ADR.sub.2, and ADR.sub.n are d.sub.1, d.sub.2, and d.sub.n, respectively. Note, transition time dn is significantly longer than transition time d.sub.1. Thus, if the memory device is enabled at the rising edge 102 of the CLK signal, it is likely that some of the ADR signals have not transitioned when the memory device is then activated. Thus, data may then be read from or written to an erroneous memory location within the memory device.
Another conventional approach is to enable the memory device at the falling edge 104 of the CLK signal. Although this approach gives the ADR signals enough time to transition, this approach may not provide enough time to decode the ADR signals, activate the memory device and perform a read or a write operation. In other words, the ADR signals may begin to transition to a new value (e.g., at the CLK signal's next rising edge 106) before the read or write operation is finished, and the possibility of an erroneous read or write is thereby increased. For memory device designs that take longer than a half cycle of the CLK signal to perform a read or a write operation, this enabling approach may be inadequate.
In view of the foregoing, there is a need for an enabling mechanism and technique that provides adequate time for the ADR signals to transition to stable values, while providing enough time for the memory device to be activated and perform a read or a write operation after the ADR signals stabilize and before the ADR signals transition to new values.